Computer Organization and Design RISC-V Edition

Computer Organization and Design RISC-V Edition

by David A. Patterson, John L. Hennessy
Released May 2017
Publisher(s): Morgan Kaufmann
ISBN: 9780128122761

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Book description

The new RISC-V Edition of Computer Organization and Design features the RISC-V open source instruction set architecture, the first open source architecture designed to be used in modern computing environments such as cloud computing, mobile devices, and other embedded systems.

With the post-PC era now upon us, Computer Organization and Design moves forward to explore this generational change with examples, exercises, and material highlighting the emergence of mobile computing and the Cloud. Updated content featuring tablet computers, Cloud infrastructure, and the x86 (cloud computing) and ARM (mobile computing devices) architectures is included.

An online companion Web site provides advanced content for further study, appendices, glossary, references, and recommended reading.

  • Features RISC-V, the first such architecture designed to be used in modern computing environments, such as cloud computing, mobile devices, and other embedded systems
  • Includes relevant examples, exercises, and material highlighting the emergence of mobile computing and the cloud

Table of contents

  1. Cover image
  2. Title page
  3. Table of Contents
  4. In Praise of Computer Organization and Design: The Hardware/Software Interface
  5. Copyright
  6. Dedication
  7. Acknowledgments
  8. Preface
    1. About This Book
    2. About the Other Book
    3. Why RISC-V for This Edition?
    4. Changes for the Fifth Edition
    5. Instructor Support
    6. Concluding Remarks
    7. Acknowledgments
  9. 1. Computer Abstractions and Technology
    1. Abstract
    2. 1.1 Introduction
    3. 1.2 Eight Great Ideas in Computer Architecture
    4. 1.3 Below Your Program
    5. 1.4 Under the Covers
    6. 1.5 Technologies for Building Processors and Memory
    7. 1.6 Performance
    8. 1.7 The Power Wall
    9. 1.8 The Sea Change: The Switch from Uniprocessors to Multiprocessors
    10. 1.9 Real Stuff: Benchmarking the Intel Core i7
    11. 1.10 Fallacies and Pitfalls
    12. 1.11 Concluding Remarks
    13. Historical Perspective and Further Reading
    14. 1.12 Historical Perspective and Further Reading
    15. 1.13 Exercises
  10. 2. Instructions: Language of the Computer
    1. Abstract
    2. 2.1 Introduction
    3. 2.2 Operations of the Computer Hardware
    4. 2.3 Operands of the Computer Hardware
    5. 2.4 Signed and Unsigned Numbers
    6. 2.5 Representing Instructions in the Computer
    7. 2.6 Logical Operations
    8. 2.7 Instructions for Making Decisions
    9. 2.8 Supporting Procedures in Computer Hardware
    10. 2.9 Communicating with People
    11. 2.10 RISC-V Addressing for Wide Immediates and Addresses
    12. 2.11 Parallelism and Instructions: Synchronization
    13. 2.12 Translating and Starting a Program
    14. 2.13 A C Sort Example to Put it All Together
    15. 2.14 Arrays versus Pointers
    16. Advanced Material: Compiling C and Interpreting Java
    17. 2.15 Advanced Material: Compiling C and Interpreting Java
    18. 2.16 Real Stuff: MIPS Instructions
    19. 2.17 Real Stuff: x86 Instructions
    20. 2.18 Real Stuff: The Rest of the RISC-V Instruction Set
    21. 2.19 Fallacies and Pitfalls
    22. 2.20 Concluding Remarks
    23. Historical Perspective and Further Reading
    24. 2.22 Historical Perspective and Further Reading
    25. 2.22 Exercises
  11. 3. Arithmetic for Computers
    1. Abstract
    2. 3.1 Introduction
    3. 3.2 Addition and Subtraction
    4. 3.3 Multiplication
    5. 3.4 Division
    6. 3.5 Floating Point
    7. 3.6 Parallelism and Computer Arithmetic: Subword Parallelism
    8. 3.7 Real Stuff: Streaming SIMD Extensions and Advanced Vector Extensions in x86
    9. 3.8 Going Faster: Subword Parallelism and Matrix Multiply
    10. 3.9 Fallacies and Pitfalls
    11. 3.10 Concluding Remarks
    12. Historical Perspective and Further Reading
    13. Historical Perspective and Further Reading
    14. 3.12 Exercises
  12. 4. The Processor
    1. Abstract
    2. 4.1 Introduction
    3. 4.2 Logic Design Conventions
    4. 4.3 Building a Datapath
    5. 4.4 A Simple Implementation Scheme
    6. 4.5 An Overview of Pipelining
    7. 4.6 Pipelined Datapath and Control
    8. 4.7 Data Hazards: Forwarding versus Stalling
    9. 4.8 Control Hazards
    10. 4.9 Exceptions
    11. 4.10 Parallelism via Instructions
    12. 4.11 Real Stuff: The ARM Cortex-A53 and Intel Core i7 Pipelines
    13. 4.12 Going Faster: Instruction-Level Parallelism and Matrix Multiply
    14. Advanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations
    15. 4.13 Advanced Topic: An Introduction to Digital Design Using a Hardware Design Language to Describe and Model a Pipeline and More Pipelining Illustrations
    16. 4.14 Fallacies and Pitfalls
    17. 4.15 Concluding Remarks
    18. Historical Perspective and Further Reading
    19. 4.16 Historical Perspective and Further Reading
    20. 4.17 Exercises
  13. 5. Large and Fast: Exploiting Memory Hierarchy
    1. Abstract
    2. 5.1 Introduction
    3. 5.2 Memory Technologies
    4. 5.3 The Basics of Caches
    5. 5.4 Measuring and Improving Cache Performance
    6. 5.5 Dependable Memory Hierarchy
    7. 5.6 Virtual Machines
    8. 5.7 Virtual Memory
    9. 5.8 A Common Framework for Memory Hierarchy
    10. 5.9 Using a Finite-State Machine to Control a Simple Cache
    11. 5.10 Parallelism and Memory Hierarchy: Cache Coherence
    12. Parallelism and Memory Hierarchy: Redundant Arrays of Inexpensive Disks
    13. 5.11 Parallelism and Memory Hierarchy: Redundant Arrays of Inexpensive Disks
    14. Advanced Material: Implementing Cache Controllers
    15. 5.12 Advanced Material: Implementing Cache Controllers
    16. 5.13 Real Stuff: The ARM Cortex-A53 and Intel Core i7 Memory Hierarchies
    17. 5.14 Real Stuff: The Rest of the RISC-V System and Special Instructions
    18. 5.15 Going Faster: Cache Blocking and Matrix Multiply
    19. 5.16 Fallacies and Pitfalls
    20. 5.17 Concluding Remarks
    21. Historical Perspective and Further Reading
    22. 5.18 Historical Perspective and Further Reading
    23. 5.19 Exercises
  14. 6. Parallel Processors from Client to Cloud
    1. Abstract
    2. 6.1 Introduction
    3. 6.2 The Difficulty of Creating Parallel Processing Programs
    4. 6.3 SISD, MIMD, SIMD, SPMD, and Vector
    5. 6.4 Hardware Multithreading
    6. 6.5 Multicore and Other Shared Memory Multiprocessors
    7. 6.6 Introduction to Graphics Processing Units
    8. 6.7 Clusters, Warehouse Scale Computers, and Other Message-Passing Multiprocessors
    9. 6.8 Introduction to Multiprocessor Network Topologies
    10. Communicating to the Outside World: Cluster Networking
    11. 6.9 Communicating to the Outside World: Cluster Networking
    12. 6.10 Multiprocessor Benchmarks and Performance Models
    13. 6.11 Real Stuff: Benchmarking and Rooflines of the Intel Core i7 960 and the NVIDIA Tesla GPU
    14. 6.12 Going Faster: Multiple Processors and Matrix Multiply
    15. 6.13 Fallacies and Pitfalls
    16. 6.14 Concluding Remarks
    17. Historical Perspective and Further Reading
    18. 6.15 Historical Perspective and Further Reading
    19. 6.16 Exercises
  15. Appendix
    1. Appendix A. The Basics of Logic Design
      1. A.1 Introduction
      2. A.2 Gates, Truth Tables, and Logic Equations
      3. A.3 Combinational Logic
      4. A.4 Using a Hardware Description Language
      5. A.5 Constructing a Basic Arithmetic Logic Unit
      6. A.6 Faster Addition: Carry Lookahead
      7. A.7 Clocks
      8. A.8 Memory Elements: Flip-Flops, Latches, and Registers
      9. A.9 Memory Elements: SRAMs and DRAMs
      10. A.10 Finite-State Machines
      11. A.11 Timing Methodologies
      12. A.12 Field Programmable Devices
      13. A.13 Concluding Remarks
      14. A.14 Exercises
    2. Appendix B. Graphics and Computing GPUs
      1. B.1 Introduction
      2. B.2 GPU System Architectures
      3. B.3 Programming GPUs
      4. B.4 Multithreaded Multiprocessor Architecture
      5. B.5 Parallel Memory System
      6. B.6 Floating-point Arithmetic
      7. B.7 Real Stuff: The NVIDIA GeForce 8800
      8. B.8 Real Stuff: Mapping Applications to GPUs
      9. B.9 Fallacies and Pitfalls
      10. B.10 Concluding Remarks
      11. B.11 Historical Perspective and Further Reading
      12. Further Reading
    3. Appendix C. Mapping Control to Hardware
      1. C.1 Introduction
      2. C.2 Implementing Combinational Control Units
      3. C.3 Implementing Finite-State Machine Control
      4. C.4 Implementing the Next-State Function with a Sequencer
      5. C.5 Translating a Microprogram to Hardware
      6. C.6 Concluding Remarks
      7. C.7 Exercises
    4. Appendix D. A Survey of RISC Architectures for Desktop, Server, and Embedded Computers
      1. D.1 Introduction
      2. D.2 Addressing Modes and Instruction Formats
      3. D.3 Instructions: The MIPS Core Subset
      4. D.4 Instructions: Multimedia Extensions of the Desktop/Server RISCs
      5. D.5 Instructions: Digital Signal-Processing Extensions of the Embedded RISCs
      6. D.6 Instructions: Common Extensions to MIPS Core
      7. D.7 Instructions Unique to MIPS-64
      8. D.8 Instructions Unique to Alpha
      9. D.9 Instructions Unique to SPARC v9
      10. D.10 Instructions Unique to PowerPC
      11. D.11 Instructions Unique to PA-RISC 2.0
      12. D.12 Instructions Unique to ARM
      13. D.13 Instructions Unique to Thumb
      14. D.14 Instructions Unique to SuperH
      15. D.15 Instructions Unique to M32R
      16. D.16 Instructions Unique to MIPS-16
      17. D.17 Concluding Remarks
      18. Further Reading
  16. Answers to Check Yourself
    1. Chapter 1
    2. Chapter 2
    3. Chapter 3
    4. Chapter 4
    5. Chapter 5
    6. Chapter 6
  17. Glossary
  18. Further Reading
  19. Index
  20. RISC-V Reference Data Card (“Green Card”)

Product information

  • Title: Computer Organization and Design RISC-V Edition
  • Author(s): David A. Patterson, John L. Hennessy
  • Release date: May 2017
  • Publisher(s): Morgan Kaufmann
  • ISBN: 9780128122761