Analog Integrated Circuit Design, 2nd Edition

Analog Integrated Circuit Design, 2nd Edition

by Tony Chan Carusone, David A. Johns, Kenneth W. Martin
Released December 2011
Publisher(s): Wiley
ISBN: 9780470770108

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Book description

The 2nd Edition of Analog Integrated Circuit Design focuses on more coverage about several types of circuits that have increased in importance in the past decade. Furthermore, the text is enhanced with material on CMOS IC device modeling, updated processing layout and expanded coverage to reflect technical innovations. CMOS devices and circuits have more influence in this edition as well as a reduced amount of text on BiCMOS and bipolar information. New chapters include topics on frequency response of analog ICs and basic theory of feedback amplifiers.

Table of contents

  1. Coverpage
  2. Titlepage
  3. Copyright
  4. Dedication
  5. Preface
  6. Contents
  7. Chapter 1 Integrated-Circuit Devices and Modelling
    1. 1.1 Semiconductors and pn Junctions
      1. 1.1.1 Diodes
      2. 1.1.2 Reverse-Biased Diodes
      3. 1.1.3 Graded Junctions
      4. 1.1.4 Large-Signal Junction Capacitance
      5. 1.1.5 Forward-Biased Junctions
      6. 1.1.6 Junction Capacitance of Forward-Biased Diode
      7. 1.1.7 Small-Signal Model of a Forward-Biased Diode
      8. 1.1.8 Schottky Diodes
    2. 1.2 MOS Transistors
      1. 1.2.1 Symbols for MOS Transistors
      2. 1.2.2 Basic Operation
      3. 1.2.3 Large-Signal Modelling
      4. 1.2.4 Body Effect
      5. 1.2.5 p-Channel Transistors
      6. 1.2.6 Low-Frequency Small-Signal Modelling in the Active Region
      7. 1.2.7 High-Frequency Small-Signal Modelling in the Active Region
      8. 1.2.8 Small-Signal Modelling in the Triode and Cutoff Regions
      9. 1.2.9 Analog Figures of Merit and Trade-offs
    3. 1.3 Device Model Summary
      1. 1.3.1 Constants
      2. 1.3.2 Diode Equations
      3. 1.3.3 MOS Transistor Equations
    4. 1.4 Advanced MOS Modelling
      1. 1.4.1 Subthreshold Operation
      2. 1.4.2 Mobility Degradation
      3. 1.4.3 Summary of Subthreshold and Mobility Degradation Equations
      4. 1.4.4 Parasitic Resistances
      5. 1.4.5 Short-Channel Effects
      6. 1.4.6 Leakage Currents
    5. 1.5 SPICE Modelling Parameters
      1. 1.5.1 Diode Model
      2. 1.5.2 MOS Transistors
      3. 1.5.3 Advanced SPICE Models of MOS Transistors
    6. 1.6 Passive Devices
      1. 1.6.1 Resistors
      2. 1.6.2 Capacitors
    7. 1.7 Appendix
      1. 1.7.1 Diode Exponential Relationship
      2. 1.7.2 Diode-Diffusion Capacitance
      3. 1.7.3 MOS Threshold Voltage and the Body Effect
      4. 1.7.4 MOS Triode Relationship
    8. 1.8 Key Points
    9. 1.9 References
    10. 1.10 Problems
  8. Chapter 2 Processing and Layout
    1. 2.1 CMOS Processing
      1. 2.1.1 The Silicon Wafer
      2. 2.1.2 Photolithography and Well Definition
      3. 2.1.3 Diffusion and Ion Implantation
      4. 2.1.4 Chemical Vapor Deposition and Defining the Active Regions
      5. 2.1.5 Transistor Isolation
      6. 2.1.6 Gate-Oxide and Threshold-Voltage Adjustments
      7. 2.1.7 Polysilicon Gate Formation
      8. 2.1.8 Implanting the Junctions, Depositing SiO2, and Opening Contact Holes
      9. 2.1.9 Annealing, Depositing and Patterning Metal, and Overglass Deposition
      10. 2.1.10 Additional Processing Steps
    2. 2.2 CMOS Layout and Design Rules
      1. 2.2.1 Spacing Rulesy
      2. 2.2.2 Planarity and Fill Requirements
      3. 2.2.3 Antenna Rules
      4. 2.2.4 Latch-Up
    3. 2.3 Variability and Mismatch
      1. 2.3.1 Systematic Variations Including Proximity Effects
      2. 2.3.2 Process Variations
      3. 2.3.3 Random Variations and Mismatch
    4. 2.4 Analog Layout Considerations
      1. 2.4.1 Transistor Layouts
      2. 2.4.2 Capacitor Matching
      3. 2.4.3 Resistor Layout
      4. 2.4.4 Noise Considerations
    5. 2.5 Key Points
    6. 2.6 References
    7. 2.7 Problems
  9. Chapter 3 Basic Current Mirrors and Single-Stage Amplifiers
    1. 3.1 Simple CMOS Current Mirror
    2. 3.2 Common-Source Amplifier
    3. 3.3 Source-Follower or Common-Drain Amplifier
    4. 3.4 Common-Gate Amplifier
    5. 3.5 Source-Degenerated Current Mirrors
    6. 3.6 Cascode Current Mirrors
    7. 3.7 Cascode Gain Stage
    8. 3.8 MOS Differential Pair and Gain Stage
    9. 3.9 Key Points
    10. 3.10 References
    11. 3.11 Problems
  10. Chapter 4 Frequency Response of Electronic Circuits
    1. 4.1 Frequency Response of Linear Systems
      1. 4.1.1 Magnitude and Phase Response
      2. 4.1.2 First-Order Circuits
      3. 4.1.3 Second-Order Low-Pass Transfer Functions with Real Poles
      4. 4.1.4 Bode Plots
      5. 4.1.5 Second-Order Low-Pass Transfer Functions with Complex Poles
    2. 4.2 Frequency Response of Elementary Transistor Circuits
      1. 4.2.1 High-Frequency MOS Small-Signal Model
      2. 4.2.2 Common-Source Amplifier
      3. 4.2.3 Miller Theorem and Miller Effect
      4. 4.2.4 Zero-Value Time-Constant Analysis
      5. 4.2.5 Common-Source Design Examples
      6. 4.2.6 Common-Gate Amplifier
    3. 4.3 Cascode Gain Stage
    4. 4.4 Source-Follower Amplifier
    5. 4.5 Differential Pair
      1. 4.5.1 High-Frequency T-Model
      2. 4.5.2 Symmetric Differential Amplifier
      3. 4.5.3 Single-Ended Differential Amplifier
      4. 4.5.4 Differential Pair with Active Load
    6. 4.6 Key Points
    7. 4.7 References
    8. 4.8 Problems
  11. Chapter 5 Feedback Amplifiers
    1. 5.1 Ideal Model of Negative Feedback
      1. 5.1.1 Basic Definitions
      2. 5.1.2 Gain Sensitivity
      3. 5.1.3 Bandwidth
      4. 5.1.4 Linearity
      5. 5.1.5 Summary
    2. 5.2 Dynamic Response of Feedback Amplifiers
      1. 5.2.1 Stability Criteria
      2. 5.2.2 Phase Margin
    3. 5.3 First- and Second-Order Feedback Systems
      1. 5.3.1 First-Order Feedback Systems
      2. 5.3.2 Second-Order Feedback Systems
      3. 5.3.3 Higher-Order Feedback Systems
    4. 5.4 Common Feedback Amplifiers
      1. 5.4.1 Obtaining the Loop Gain, L(s)
      2. 5.4.2 Non-Inverting Amplifier
      3. 5.4.3 Transimpedance (Inverting) Amplifiers
    5. 5.5 Summary of Key Points
    6. 5.6 References
    7. 5.7 Problems
  12. Chapter 6 Basic Opamp Design and Compensation
    1. 6.1 Two-Stage CMOS Opamp
      1. 6.1.1 Opamp Gain
      2. 6.1.2 Frequency Response
      3. 6.1.3 Slew Rate
      4. 6.1.4 n-Channel or p-Channel Input Stage
      5. 6.1.5 Systematic Offset Voltage
    2. 6.2 Opamp Compensation
      1. 6.2.1 Dominant-Pole Compensation and Lead Compensation
      2. 6.2.2 Compensating the Two-Stage Opamp
      3. 6.2.3 Making Compensation Independent of Process and Temperature
    3. 6.3 Advanced Current Mirrors
      1. 6.3.1 Wide-Swing Current Mirrors
      2. 6.3.2 Enhanced Output-Impedance Current Mirrors and Gain Boosting
      3. 6.3.3 Wide-Swing Current Mirror with Enhanced Output Impedance
      4. 6.3.4 Current-Mirror Symbol
    4. 6.4 Folded-Cascode Opamp
      1. 6.4.1 Small-Signal Analysis
      2. 6.4.2 Slew Rate
    5. 6.5 Current Mirror Opamp
    6. 6.6 Linear Settling Time Revisited
    7. 6.7 Fully Differential Opamps
      1. 6.7.1 Fully Differential Folded-Cascode Opamp
      2. 6.7.2 Alternative Fully Differential Opamps
      3. 6.7.3 Low Supply Voltage Opamps
    8. 6.8 Common-Mode Feedback Circuits
    9. 6.9 Summary of Key Points
    10. 6.10 References
    11. 6.11 Problems
  13. Chapter 7 Biasing, References, and Regulators
    1. 7.1 Analog Integrated Circuit Biasing
      1. 7.1.1 Bias Circuits
      2. 7.1.2 Reference Circuits
      3. 7.1.3 Regulator Circuits
    2. 7.2 Establishing Constant Transconductance
      1. 7.2.1 Basic Constant-Transconductance Circuit
      2. 7.2.2 Improved Constant-Transconductance Circuits
    3. 7.3 Establishing Constant Voltages and Currents
      1. 7.3.1 Bandgap Voltage Reference Basics
      2. 7.3.2 Circuits for Bandgap References
      3. 7.3.3 Low-Voltage Bandgap Reference
      4. 7.3.4 Current Reference
    4. 7.4 Voltage Regulation
      1. 7.4.1 Regulator Specifications
      2. 7.4.2 Feedback Analysis
      3. 7.4.3 Low Dropout Regulators
    5. 7.5 Summary of Key Points
    6. 7.6 References
    7. 7.7 Problems
  14. Chapter 8 Bipolar Devices and Circuits
    1. 8.1 Bipolar-Junction Transistors
      1. 8.1.1 Basic Operation
      2. 8.1.2 Analog Figures of Merit
    2. 8.2 Bipolar Device Model Summary
    3. 8.3 SPICE Modeling
    4. 8.4 Bipolar and BICMOS Processing
      1. 8.4.1 Bipolar Processing
      2. 8.4.2 Modern SiGe BiCMOS HBT Processing
      3. 8.4.3 Mismatch in Bipolar Devices
    5. 8.5 Bipolar Current Mirrors and Gain Stages
      1. 8.5.1 Current Mirrors
      2. 8.5.2 Emitter Follower
      3. 8.5.3 Bipolar Differential Pair
    6. 8.6 Appendix
      1. 8.6.1 Bipolar Transistor Exponential Relationship
      2. 8.6.2 Base Charge Storage of an Active BJT
    7. 8.7 Summary of Key Points
    8. 8.8 References
    9. 8.9 Problems
  15. Chapter 9 Noise and Linearity Analysis and Modelling
    1. 9.1 Time-Domain Analysis
      1. 9.1.1 Root Mean Square (rms) Value
      2. 9.1.2 SNR
      3. 9.1.3 Units of dBm
      4. 9.1.4 Noise Summation
    2. 9.2 Frequency-Domain Analysis
      1. 9.2.1 Noise Spectral Density
      2. 9.2.2 White Noise
      3. 9.2.3 1/f, or Flicker, Noise
      4. 9.2.4 Filtered Noise
      5. 9.2.5 Noise Bandwidth
      6. 9.2.6 Piecewise Integration of Noise
      7. 9.2.7 1/f Noise Tangent Principle
    3. 9.3 Noise Models for Circuit Elements
      1. 9.3.1 Resistors
      2. 9.3.2 Diodes
      3. 9.3.3 Bipolar Transistors
      4. 9.3.4 MOSFETS
      5. 9.3.5 Opamps
      6. 9.3.6 Capacitors and Inductors
      7. 9.3.7 Sampled Signal Noise
      8. 9.3.8 Input-Referred Noise
    4. 9.4 Noise Analysis Examples
      1. 9.4.1 Opamp Example
      2. 9.4.2 Bipolar Common-Emitter Example
      3. 9.4.3 CMOS Differential Pair Example
      4. 9.4.4 Fiber-Optic Transimpedance Amplifier Example
    5. 9.5 Dynamic Range Performance
      1. 9.5.1 Total Harmonic Distortion (THD)
      2. 9.5.2 Third-Order Intercept Point (IP3)
      3. 9.5.3 Spurious-Free Dynamic Range (SFDR)
      4. 9.5.4 Signal-to-Noise and Distortion Ratio (SNDR)
    6. 9.6 Key Points
    7. 9.7 References
    8. 9.8 Problems
  16. Chapter 10 Comparators
    1. 10.1 Comparator Specifications
      1. 10.1.1 Input Offset and Noise
      2. 10.1.2 Hysteresis
    2. 10.2 Using an Opamp for a Comparator
      1. 10.2.1 Input-Offset Voltage Errors
    3. 10.3 Charge-Injection Errors
      1. 10.3.1 Making Charge-Injection Signal Independent
      2. 10.3.2 Minimizing Errors Due to Charge-Injection
      3. 10.3.3 Speed of Multi-Stage Comparators
    4. 10.4 Latched Comparators
      1. 10.4.1 Latch-Mode Time Constant
      2. 10.4.2 Latch Offset
    5. 10.5 Examples of CMOS and BiCMOS Comparators
      1. 10.5.1 Input-Transistor Charge Trapping
    6. 10.6 Examples of Bipolar Comparators
    7. 10.7 Key Points
    8. 10.8 References
    9. 10.9 Problems
  17. Chapter 11 Sample-and-Hold and Translinear Circuits
    1. 11.1 Performance of Sample-and-Hold Circuits
      1. 11.1.1 Testing Sample and Holds
    2. 11.2 MOS Sample-and-Hold Basics
    3. 11.3 Examples of CMOS S/H Circuits
    4. 11.4 Bipolar and BiCMOS Sample-and-Holds
    5. 11.5 Translinear Gain Cell
    6. 11.6 Translinear Multiplier
    7. 11.7 Key Points
    8. 11.8 References
    9. 11.9 Problems
  18. Chapter 12 Continuous-Time Filters
    1. 12.1 Introduction to Continuous-Time Filters
      1. 12.1.1 First-Order Filters
      2. 12.1.2 Second-Order Filters
    2. 12.2 Introduction to Gm-C Filters
      1. 12.2.1 Integrators and Summers
      2. 12.2.2 Fully Differential Integrators
      3. 12.2.3 First-Order Filter
      4. 12.2.4 Biquad Filter
    3. 12.3 Transconductors Using Fixed Resistors
    4. 12.4 CMOS Transconductors Using Triode Transistors
      1. 12.4.1 Transconductors Using a Fixed-Bias Triode Transistor
      2. 12.4.2 Transconductors Using Varying Bias-Triode Transistors
      3. 12.4.3 Transconductors Using Constant Drain-Source Voltages
    5. 12.5 CMOS Transconductors Using Active Transistors
      1. 12.5.1 CMOS Pair
      2. 12.5.2 Constant Sum of Gate-Source Voltages
      3. 12.5.3 Source-Connected Differential Pair
      4. 12.5.4 Inverter-Based
      5. 12.5.5 Differential-Pair with Floating Voltage Sources
      6. 12.5.6 Bias-Offset Cross-Coupled Differential Pairs
    6. 12.6 Bipolar Transconductors
      1. 12.6.1 Gain-Cell Transconductors
      2. 12.6.2 Transconductors Using Multiple Differential Pairs
    7. 12.7 BiCMOS Transconductors
      1. 12.7.1 Tunable MOS in Triode
      2. 12.7.2 Fixed-Resistor Transconductor with a Translinear Multiplier
      3. 12.7.3 Fixed Active MOS Transconductor with a Translinear Multiplier
    8. 12.8 Active RC and MOSFET-C Filters
      1. 12.8.1 Active RC Filters
      2. 12.8.2 MOSFET-C Two-Transistor Integrators
      3. 12.8.3 Four-Transistor Integrators
      4. 12.8.4 R-MOSFET-C Filters
    9. 12.9 Tuning Circuitry
      1. 12.9.1 Tuning Overview
      2. 12.9.2 Constant Transconductance
      3. 12.9.3 Frequency Tuning
      4. 12.9.4 Q-Factor Tuning
      5. 12.9.5 Tuning Methods Based on Adaptive Filtering
    10. 12.10 Introduction to Complex Filters
      1. 12.10.1 Complex Signal Processing
      2. 12.10.2 Complex Operations
      3. 12.10.3 Complex Filters
      4. 12.10.4 Frequency-Translated Analog Filters
    11. 12.11 Key Points
    12. 12.12 References
    13. 12.13 Problems
  19. Chapter 13 Discrete-Time Signals
    1. 13.1 Overview of Some Signal Spectra
    2. 13.2 Laplace Transforms of Discrete-Time Signals
      1. 13.2.1 Spectra of Discrete-Time Signals
    3. 13.3 z-Transform
    4. 13.4 Downsampling and Upsampling
    5. 13.5 Discrete-Time Filters
      1. 13.5.1 Frequency Response of Discrete-Time Filters
      2. 13.5.2 Stability of Discrete-Time Filters
      3. 13.5.3 IIR and FIR Filters
      4. 13.5.4 Bilinear Transform
    6. 13.6 Sample-and-Hold Response
    7. 13.7 Key Points
    8. 13.8 References
    9. 13.9 Problems
  20. Chapter 14 Switched-Capacitor Circuits
    1. 14.1 Basic Building Blocks
      1. 14.1.1 Opamps
      2. 14.1.2 Capacitors
      3. 14.1.3 Switches
      4. 14.1.4 Nonoverlapping Clocks
    2. 14.2 Basic Operation and Analysis
      1. 14.2.1 Resistor Equivalence of a Switched Capacitor
      2. 14.2.2 Parasitic-Sensitive Integrator
      3. 14.2.3 Parasitic-Insensitive Integrators
      4. 14.2.4 Signal-Flow-Graph Analysis
    3. 14.3 Noise in Switched-Capacitor Circuits
    4. 14.4 First-Order Filters
      1. 14.4.1 Switch Sharing
      2. 14.4.2 Fully Differential Filters
    5. 14.5 Biquad Filters
      1. 14.5.1 Low-Q Biquad Filter
      2. 14.5.2 High-Q Biquad Filter
    6. 14.6 Charge Injection
    7. 14.7 Switched-Capacitor Gain Circuits
      1. 14.7.1 Parallel Resistor-Capacitor Circuit
      2. 14.7.2 Resettable Gain Circuit
      3. 14.7.3 Capacitive-Reset Gain Circuit
    8. 14.8 Correlated Double-Sampling Techniques
    9. 14.9 Other Switched-Capacitor Circuits
      1. 14.9.1 Amplitude Modulator
      2. 14.9.2 Full-Wave Rectifier
      3. 14.9.3 Peak Detectors
      4. 14.9.4 Voltage-Controlled Oscillator
      5. 14.9.5 Sinusoidal Oscillator
    10. 14.10 Key Points
    11. 14.11 References
    12. 14.12 Problems
  21. Chapter 15 Data Converter Fundamentals
    1. 15.1 Ideal D/A Converter
    2. 15.2 Ideal A/D Converter
    3. 15.3 Quantization Noise
      1. 15.3.1 Deterministic Approach
      2. 15.3.2 Stochastic Approach
    4. 15.4 Signed Codes
    5. 15.5 Performance Limitations
      1. 15.5.1 Resolution
      2. 15.5.2 Offset and Gain Error
      3. 15.5.3 Accuracy and Linearity
    6. 15.6 Key Points
    7. 15.7 References
    8. 15.8 Problems
  22. Chapter 16 Nyquist-Rate D/A Converters
    1. 16.1 Decoder-Based Converters
      1. 16.1.1 Resistor String Converters
      2. 16.1.2 Folded Resistor-String Converters
      3. 16.1.3 Multiple Resistor-String Converters
      4. 16.1.4 Signed Outputs
    2. 16.2 Binary-Scaled Converters
      1. 16.2.1 Binary-Weighted Resistor Converters
      2. 16.2.2 Reduced-Resistance-Ratio Ladders
      3. 16.2.3 R-2R-Based Converters
      4. 16.2.4 Charge-Redistribution Switched-Capacitor Converters
      5. 16.2.5 Current-Mode Converters
      6. 16.2.6 Glitches
    3. 16.3 Thermometer-Code Converters
      1. 16.3.1 Thermometer-Code Current-Mode D/A Converters
      2. 16.3.2 Single-Supply Positive-Output Converters
      3. 16.3.3 Dynamically Matched Current Sources
    4. 16.4 Hybrid Converters
      1. 16.4.1 Resistor-Capacitor Hybrid Converters
      2. 16.4.2 Segmented Converters
    5. 16.5 Key Points
    6. 16.6 References
    7. 16.7 Problems
  23. Chapter 17 Nyquist-Rate A/D Converters
    1. 17.1 Integrating Converters
    2. 17.2 Successive-Approximation Converters
      1. 17.2.1 DAC-Based Successive Approximation
      2. 17.2.2 Charge-Redistribution A/D
      3. 17.2.3 Resistor-Capacitor Hybrid
      4. 17.2.4 Speed Estimate for Charge-Redistribution Converters
      5. 17.2.5 Error Correction in Successive-Approximation Converters
      6. 17.2.6 Multi-Bit Successive-Approximation
    3. 17.3 Algorithmic (or Cyclic) A/D Converter
      1. 17.3.1 Ratio-Independent Algorithmic Converter
    4. 17.4 Pipelined A/D Converters
      1. 17.4.1 One-Bit-Per-Stage Pipelined Converter
      2. 17.4.2 1.5 Bit Per Stage Pipelined Converter
      3. 17.4.3 Pipelined Converter Circuits
      4. 17.4.4 Generalized k-Bit-Per-Stage Pipelined Converters
    5. 17.5 Flash Converters
      1. 17.5.1 Issues in Designing Flash A/D Converters
    6. 17.6 Two-Step A/D Converters
      1. 17.6.1 Two-Step Converter with Digital Error Correction
    7. 17.7 Interpolating A/D Converters
    8. 17.8 Folding A/D Converters
    9. 17.9 Time-Interleaved A/D Converters
    10. 17.10 Key Points
    11. 17.11 References
    12. 17.12 Problems
  24. Chapter 18 Oversampling Converters
    1. 18.1 Oversampling without Noise Shaping
      1. 18.1.1 Quantization Noise Modelling
      2. 18.1.2 White Noise Assumption
      3. 18.1.3 Oversampling Advantage
      4. 18.1.4 The Advantage of 1-Bit D/A Converters
    2. 18.2 Oversampling with Noise Shaping
      1. 18.2.1 Noise-Shaped Delta-Sigma Modulator
      2. 18.2.2 First-Order Noise Shaping
      3. 18.2.3 Switched-Capacitor Realization of a First-Order A/D Converter
      4. 18.2.4 Second-Order Noise Shaping
      5. 18.2.5 Noise Transfer-Function Curves
      6. 18.2.6 Quantization Noise Power of 1-Bit Modulators
      7. 18.2.7 Error-Feedback Structure
    3. 18.3 System Architectures
      1. 18.3.1 System Architecture of Delta-Sigma A/D Converters
      2. 18.3.2 System Architecture of Delta-Sigma D/A Converters
    4. 18.4 Digital Decimation Filters
      1. 18.4.1 Multi-Stage
      2. 18.4.2 Single Stage
    5. 18.5 Higher-Order Modulators
      1. 18.5.1 Interpolative Architecture
      2. 18.5.2 Multi-Stage Noise Shaping (MASH) Architecture
    6. 18.6 Bandpass Oversampling Converters
    7. 18.7 Practical Considerations
      1. 18.7.1 Stability
      2. 18.7.2 Linearity of Two-Level Converters
      3. 18.7.3 Idle Tones
      4. 18.7.4 Dithering
      5. 18.7.5 Opamp Gain
    8. 18.8 Multi-Bit Oversampling Converters
      1. 18.8.1 Dynamic Element Matching
      2. 18.8.2 Dynamically Matched Current Source D/S Converters
      3. 18.8.3 Digital Calibration A/D Converter
      4. 18.8.4 A/D with Both Multi-Bit and Single-Bit Feedback
    9. 18.9 Third-Order A/D Design Example
    10. 18.10 Key Points
    11. 18.11 References
    12. 18.12 Problems
  25. Chapter 19 Phase-Locked Loops
    1. 19.1 Basic Phase-Locked Loop Architecture
      1. 19.1.1 Voltage Controlled Oscillator
      2. 19.1.2 Divider
      3. 19.1.3 Phase Detector
      4. 19.1.4 Loop Filer
      5. 19.1.5 The PLL in Lock
    2. 19.2 Linearized Small-Signal Analysis
      1. 19.2.1 Second-Order PLL Model
      2. 19.2.2 Limitations of the Second-Order Small-Signal Model
      3. 19.2.3 PLL Design Example
    3. 19.3 Jitter and Phase Noise
      1. 19.3.1 Period Jitter
      2. 19.3.2 P-Cycle Jitter
      3. 19.3.3 Adjacent Period Jitter
      4. 19.3.4 Other Spectral Representations of Jitter
      5. 19.3.5 Probability Density Function of Jitter
    4. 19.4 Electronic Oscillators
      1. 19.4.1 Ring Oscillators
      2. 19.4.2 LC Oscillators
      3. 19.4.3 Phase Noise of Oscillators
    5. 19.5 Jitter and Phase Noise in PLLS
      1. 19.5.1 Input Phase Noise and Divider Phase Noise
      2. 19.5.2 VCO Phase Noise
      3. 19.5.3 Loop Filter Noise
    6. 19.6 Key Points
    7. 19.7 References
    8. 19.8 Problems
  26. Index

Product information

  • Title: Analog Integrated Circuit Design, 2nd Edition
  • Author(s): Tony Chan Carusone, David A. Johns, Kenneth W. Martin
  • Release date: December 2011
  • Publisher(s): Wiley
  • ISBN: 9780470770108