Advances in Embedded and Fan-Out Wafer Level Packaging Technologies

5NEPES’ Fan‐Out Packaging Technology from Single die, SiP to Panel‐Level Packaging

Jong Heon (Jay) Kim

nepes Corporation

5.1 Introduction

nepes Corporation’s fan‐out wafer‐level packaging (FO‐WLP) technology was first introduced in the year 2010 on a 300 mm platform, which is based on the redistributed chip package (RCP) licensed from NXP (formerly Freescale Semiconductor) using a chip‐first, face‐down concept, which is similar to most conventional FO‐WLP platforms in the industry [1–5].

Further development has been made, enhancing the process robustness and high volume mass (HVM) production capability for automotive products, mobile applications, and system solutions with multiple devices embedded and integrated. nepes’ FO‐WLP system‐in‐package (SiP) solution offers 40–90% volumetric shrink from existing modules with flexible product design to end user [6]. Numerous active or passive components could be embedded and connected in 2D or 3D via connections to the backside of an FO‐WLP package for package‐on‐package (PoP) structures typically designed for communication modules and system control applications.

5.2 Structure and Process Flow

As shown in Figures 5.1 and 5.2, nepes’ FO‐WLP is based on chip‐first technology. Embedded ground planes (EGPs) (Cu material) are placed onto adhesive tapes laminated on substrates in advance. This EGP, however, is optional depending on the necessity and the package design. Incoming wafers, regardless of size, 6, 8, 12, or even 18 in. (in ...